View ICS873033AMT_1253150.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
FEATURES
* One differential 3.3V, 5V LVPECL / ECL output * One differential PCLK, nPCLK input pair * PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Input frequency: 3.2GHz (maximum) * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input * Additive phase jitter, RMS: 0.20ps (typical) * LVPECL mode operating voltage supply range: VCC = 3.0V to 5.5V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -5.5V to -3.0V * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS873033 is a high speed, high performance Differential-to-3.3V, 5V LVPECL/ECL HiPerClockSTM Clock Generator a n d a m e m b e r o f t h e HiPerClockS TM family of High Perfor mance Clock Solutions from ICS. The ICS873033 is characterized to operate from either a 3.3V or a 5V power supply.
IC S
BLOCK DIAGRAM
RESET
PIN ASSIGNMENT
RESET PCLK nPCLK VBB 1 2 3 4 8 7 6 5 Vcc Q nQ VEE
PCLK nPCLK V BB
/4
Q nQ
ICS873033
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
ICS873033
8-Lead TSSOP, 118 mil 3mm x 3mm x 0.95mm package body G Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 873033AM www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005
1
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6, 7 8 Name RESET PCLK nPCLK VBB VEE nQ, Q VCC Input Input Input Output Power Output Power Pulldown Reset pin. Single-ended 100h LVPECL interface levels. Pulldown Clock input. Default LOW when left floating. LVPECL interface levels. Pulldown Clock input. LVPECL interface levels. Bias voltage. Negative supply pin. Differential output pair. LVPECL interface levels. Positive supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN Parameter Input Pulldown Resistor Test Conditions Minimum Typical 75 Maximum Units k
TABLE 3. TRUTH TABLE
Inputs PCLK X nPCLK X RESET LH Q L /4 Outputs nQ H /4
LH HL L LH = LOW to HIGH transistion HL = HIGH to LOW transistion
PCLK
tRR
RESET
tPW
Q
FIGURE 1. TIMING DIAGRAM
873033AM
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
6V (LVPECL mode, VEE = 0) -6V (ECL mode, VCC = 0) -0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C 112.7C/W (0 lfpm) 101.7C/W (0 m/s) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB Storage Temperature, TSTG Package Thermal Impedance, JA Package Thermal Impedance, JA
Operating Temperature Range, TA -40C to +85C
(Junction-to-Ambient) for 8 Lead SOIC (Junction-to-Ambient) for 8 Lead TSSOP
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 5.5V; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.0 Typical 3.3 Maximum 5.5 30 Units V mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference Min
2.175 1.405 2.075 1.43 1.86
-40C Typ
2.275 1.545
Max
2.38 1.68 2.36 1.765 1.98
Min
2.225 1.425 2.075 1.43 1.86
25C Typ
2.295 1.52
Max
2.37 1.615 2.36 1.765 1.98
Min
2.295 1.44 2.075 1.43 1.86
85C Typ
2.33 1.535
Max
2.365 1.63 2.36 1.765 1.98
Units
V V V V V
150 800 1200 150 800 1200 150 Peak-to-Peak Input Voltage Input High Voltage 1.2 3.3 1.2 3.3 1.2 VCMR Common Mode Range; NOTE 2, 3 Input 150 15 0 IIH PCLK, nPCLK High Current Input -10 -1 0 IIL -10 PCLK, nPCLK Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +0.3V to -2.2V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
800
1200 3. 3 150
mV
V A A
873033AM
www.icst.com/products/hiperclocks.html
3
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
-40C Typ
3.975 3.245
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference Min
3.875 3.105 3.775 3.13 3.56
Max
4.08 3.38 4.06 3.465 3.68
Min
3.925 3.125 3.775 3.13 3.56
25C Typ
3.995 3.22
Max
4.07 3.315 4.06 3.465 3.68
Min
3.995 3.14 3.775 3.13 3.56
85C Typ
4.03 3.235
Max
4.065 3.33 4.06 3.465 3.68
Units
V V V V V
150 800 1200 150 800 1200 150 Peak-to-Peak Input Voltage Input High Voltage 1.2 5 1.2 5 1.2 VCMR Common Mode Range; NOTE 2, 3 Input 150 15 0 IIH PCLK, nPCLK High Current Input -10 -1 0 IIL -10 PCLK, nPCLK Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +2V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
800
1200 5 150
mV
V A A
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V
Symbol VOH VOL VIH VIL VBB VPP Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference -40C Min
-1.125 -1.895 -1.225 -1.87 -1.44
25C Max
-0.92 -1.62 -0.94 -1.535 -1.32
85C Max
-0.93 -1.685 -0.94 -1.535 -1.32
Typ
-1.025 -1.755
Min
-1.075 -1.875 -1.225 -1.87 -1.44
Typ
-1.005 -1.78
Min
-1.005 -1.86 -1.225 -1.87 -1.44
Typ
-0.97 -1.765
Max
-0.935 -1.67 -0.94 -1.535 -1.32
Units
V V V V V
150 800 1200 150 800 1200 150 Peak-to-Peak Input Voltage Input High Voltage VEE+1.2V 0 VEE+1.2V 0 VEE+1.2V VCMR Common Mode Range; NOTE 2, 3 Input 150 150 PCLK, nPCLK IIH High Current Input -10 -10 -10 PCLK, nPCLK IIL Low Current Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
800
1200 0 150
mV
V A A
873033AM
www.icst.com/products/hiperclocks.html
4
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
OR
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V
Symbol fMAX t PD tjit(O) tRR tR/tF Parameter Input Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; 155.52MHz, Integration Range 12kHz - 20MHz; Refer to Additive Phase Jitter Section Set/Reset Recovery; NOTE 2 Output Rise/Fall Time 20% to 80% 300 Min
VCC = 3.0V TO 5.5V; VEE = 0V
-40C Typ Max 3.2 475 0.20 150 100 100 250 200 100 300 Min
25C Typ 430 0.20 100 250 200 100 Max 3.2 530 350 Min
85C Typ 450 0.20 100 250 480 Max 3.2 550
Units GHz ps ps ps ps ps
tPW Pulse Width; NOTE 3 RESET 550 480 550 480 550 All parameters are measured at f 1.7GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: See Figure 1, Timing Diagram.
873033AM
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a
0 -10 -20 -30 -40 -50 -60
ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@ 155.52MHz (12kHz to 20MHz) = 0.20ps typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
873033AM
www.icst.com/products/hiperclocks.html
6
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
VCC
nPCLK
LVPECL
nQx PCLK
V
PP
Cross Points
V
CMR
VEE
V EE
-3.5V to -1.0V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
Phase Noise Plot
nPCLK PCLK nQ Q
tPD
Noise Power
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
PROPAGATION DELAY
RMS PHASE JITTER
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
873033AM
www.icst.com/products/hiperclocks.html
7
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows an example of the differential input that can be wired to accept single ended levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin.
VCC
C1 0.1u CLK_IN
PCLK VBB nPCLK
FIGURE 3. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
873033AM
www.icst.com/products/hiperclocks.html
8
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug-
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R2 50
3.3V
3.3V Zo = 50 Ohm
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100 - 200 R6 100 - 200 Zo = 50 Ohm C2 3.3V 3.3V LVPECL Zo = 50 Ohm C1
3.3V 3.3V R3 84 R4 84 PCLK
R4 125
nPCLK
HiPerClockS PCLK/nPCLK
R1 125
R2 125
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1
3.3V 3.3V R3 1K R4 1K PCLK
R4 120
nPCLK
HiPerClockS PCL K/n PC LK
R1 120
R2 120
R1 1K
R2 1K
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 4F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
873033AM
www.icst.com/products/hiperclocks.html
9
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
125
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination. Figure 6A shows standard termination for 5V LVPECL. The termination requires matched load of 50 resistors pull down to VCC - 2V = 3V at the receiver. Figure 6B shows Thevenin equivalence of Figure 6A. In actual application where the 3V DC power supply is not available, this approached is normally used.
5V
5V 5V PECL Zo = 50 Ohm + Zo = 50 Ohm PECL
R1 125 R2 125 Zo = 50 Ohm PECL 5V R3 84 PECL Zo = 50 Ohm + R4 84
R1 50 3V
R2 50
FIGURE 6A. STANDARD 5V PECL OUTPUT TERMINATION
FIGURE 6B. 5V PECL OUTPUT TERMINATION EXAMPLE
873033AM
www.icst.com/products/hiperclocks.html
10
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS873033. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS873033 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.5V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 30mA = 165mW Power (outputs)MAX = 30.94mW/Loaded Output pair
Total Power_MAX (5.5V, with all outputs switching) = 165mW + 30.94mW = 195.94mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.196W * 103.3C/W = 105.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE JA FOR 8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. THERMAL RESISTANCE JA FOR 8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
873033AM
1
90.5C/W
2
89.8C/W
REV. A OCTOBER 19, 2005
101.7C/W
www.icst.com/products/hiperclocks.html
11
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50 VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
-0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
873033AM
www.icst.com/products/hiperclocks.html
12
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS873033 is: 165 Pin compatible with MC100EP33
873033AM
www.icst.com/products/hiperclocks.html
13
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
FOR
PACKAGE OUTLINE - M SUFFIX
8 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
873033AM
www.icst.com/products/hiperclocks.html
14
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
FOR
PACKAGE OUTLINE - G SUFFIX
8 LEAD TSSOP
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e e1 L aaa 0.40 0 --0 0.79 0.22 0.08 3.00 BASIC 4.90 BASIC 3.00 BASIC 0.65 BASIC 1.95 BASIC 0.80 8 0.10 Millimeters Minimum 8 1.10 0.15 0.97 0.38 0.23 Maximum
Reference Document: JEDEC Publication 95, MO-187
873033AM
www.icst.com/products/hiperclocks.html
15
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS873033
HIGH SPEED, /4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Marking 873033AM 873033AM 873033AL 873033AL TBD TBD TBD TBD Package 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS873033AM ICS873033AMT ICS873033AMLF ICS873033AMLFT ICS873033AG ICS873033AGT ICS873033AGLF ICS873033AGLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 873033AM
www.icst.com/products/hiperclocks.html
16
REV. A OCTOBER 19, 2005

▲Up To Search▲

Price & Availability of ICS873033AMT

	To Download ICS873033AMT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .